Auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods

Abstract

An auto precharge control signal generating circuit includes an output enable circuit that is reset in response to a precharge operation and generates an output enable signal by latching an auto precharge command signal. A delay circuit also is provided which generates a 1 clock delay signal by delaying an active period of a column bank address signal by 1 clock, and generates a 1 clock delay signal having an active period including a non-active period sufficiently between a previous column bank address signal and a present column bank address signal in case that the burst length is 1. A combining circuit generates an auto precharge control signal by combining the column bank address signal and the 1 clock delay signal in response to the output enable signal, in order to perform the auto precharge operation after delaying 2 clock from the last data input in response to a continued auto precharge burst write command. Therefore, when the burst length is 1 in case that the time from the last data input to the auto precharge is 2 clock cycles in burst write, the present invention prevents the generation of unnecessary auto precharge control signal resulting from the crossing of the 1 clock delay signal and the column bank address signal in the middle of continuous burst write operation.