The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2002

Filed:

Nov. 03, 1999
Applicant:
Inventors:

Eric John Lukes, Rochester, MN (US);

James David Strom, Rochester, MN (US);

Dana Marie Woeste, Mantorville, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/90175 ;
U.S. Cl.
CPC ...
H03K 1/90175 ;
Abstract

A CMOS signal transmission system for sending a large amount of CMOS signals into a separate quiet analog power domain. Transmission system comprises a converter sub-system which provides at least another device stage through which noise in the CMOS signals must flow and be attenuated to provide converted CMOS signals and a multiplexer coupled to the converter wherein the multiplexer receives converted CMOS signals from the converter sub-system and also receives delayed path control signals. The converter comprises a constant current source for providing a high level voltage reference and a constant current, two complimentary pass gates, and two sets of components for providing paths to ground from the constant current source through the two complimentary pass gates. When CMOS input signal is high and Complimentary CMOS input signal is low, the pass gate comprising transistors T and T is on and transistors T and T are off and connection BSEL is pulled high turning on bipolar transistor Q allowing current to flow through Q and pulling net SB low and selecting inputs B , B to be transferred to ECL Differential Outputs. Likewise, when CMOS input signal is low and Complimentary CMOS input signal is high, pass gate comprising transistors T and T is on, and transistors T and T are off, and connection ASEL is pulled high turning on bipolar transistor Q allowing current to flow through Q and pulling net SA low and selecting inputs A , A to be transferred to ECL Differential Outputs.


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