The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2002

Filed:

Apr. 13, 2000
Applicant:
Inventors:

Kenneth William Ferguson, Burnaby, CA;

Brian Gerson, Coquitlam, CA;

Assignee:

PMC-Sierra, Inc., Burnaby, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/126 ;
U.S. Cl.
CPC ...
G01R 3/126 ;
Abstract

Test device (DUT) current flow is mirrored through a capacitor. If the mirrored current is switched to bypass the capacitor, the capacitor discharges. Otherwise, the mirrored current charges the capacitor. The charging capacitor's voltage rise time is proportional to the DUT's IDDQ current. Several IDDQ reference values can be derived, each representing quiescent state operation of a defect-free copy of the DUT. An IDDQ test value is derived for each IDDQ reference value. Each test value represents quiescent state operation of the DUT after application of the test vector which produced the corresponding reference value. The reference values are compared to their corresponding test values and a plurality of scaling factors derived. Each scaling factor represents a proportionality between corresponding reference and test values. The DUT is “non-defective” if the scaling factors are equal within a predefined error range . Otherwise, the DUT is “defective”.


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