Shallow trench isolation formation without planarization mask

Abstract

A semiconductor device having shallow trench isolation (STI) is formed without dishing of the insulating material filling the trench, and without forming a planarization mask. Embodiments include forming a pad oxide layer and a polish stop layer, such as silicon nitride, on a semiconductor substrate, forming a trench in the substrate, and filling the trench with a first insulating layer, such as silicon dioxide. A second polish stop layer is then deposited on the first insulating layer, followed by a second, sacrificial insulating layer, such as silicon dioxide, to cover the second polish stop layer. The second insulating layer is then polished, as by CMP, to expose the second polish stop layer above the first polish stop layer, and the exposed portion of the second polish stop layer is then removed, as by wet etching, to expose the first insulating layer. The first and second insulating layers are then polished, as by CMP, to expose the first polish stop layer and the remaining portion of the second polish stop layer above the trench. The trench fill is planar at the trench edges and slightly higher than the main surface of the substrate, and exhibits no dishing. Thus, dishing of the trench fill is avoided without forming an expensive and complex planarization mask.