Semiconductor device and manufacturing method thereof

Abstract

An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a silicon substrate. A p type impurity concentration profile. includes respective peak concentrations at a dope region for forming a p type well, a p type channel cut region, and a p type channel dope region. An impurity concentration profile of the n type source/drain region crosses the p type impurity concentration profile at a low concentration, and includes phosphorus implantation regions indicating impurity concentrations respectively higher than those of the p type channel cut region and the p type channel dope region and respective peaks in impurity concentration at the neighborhood of respective depth thereof. The impurity concentration profile of the n type source/drain region has a minimum point or inflection point at the region between the impurity concentration peaks of the phosphorus implantation regions.