Parallel processing instructions routed through plural differing capacity units of operand address generators coupled to multi-ported memory and alus

Abstract

Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operands from the memory, the probability is high that at least one of any three program instructions to be executed at the same time need not fetch an operand from memory. The two memory ports are thus connected at any given time with the two of the three pipelines which are processing instructions that require memory access, the pipeline without access to the memory processing an instruction that does not need it. To do so, the added third pipeline need not have all the same resources as the other two pipelines, so its stages are made to have a reduced capability in order to save space and reduce power consumption. The stages of the three pipelines are also dynamically interchanged in response to the specific combination of three instructions being processed at the same time, in order to increase the rate of processing a large number of instructions.