The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2002

Filed:

Jun. 15, 2000
Applicant:
Inventor:

Katsumi Okina, Fuchu, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A semiconductor memory is provided which has a FIFO memory in which data is read in synchronization with a read clock signal. In order to read the memory, the device has a read controller which generates a read counter clock signal in synchronization with the read clock signal and a memory read access signal, and which generates a read counter reset signal which becomes active in synchronization with the read clock signal after the reset signal becomes active. The device also has a read counter which sequentially generates first read addresses whose address values are different in synchronization with the read clock signal and is reset when the read counter reset signal is active, and an AND gate group in which second read address signals are output and first read address signals from a read counter and the reset signal are input. The output of the AND gate group becomes the output from the read counter when the reset signal is HIGH, and during the reset when the reset signal is LOW, the read clock signal is set at a specified address 0 in non-synchronization with the read clock signal.


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