The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 2002
Filed:
Mar. 24, 2000
Robert D. Morrison, Star, ID (US);
Eugene A. Roylance, Boise, ID (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
An electrophotographic imaging device uses a transition placement device to position transitions in a stream of video data. A rasterizer included in the electrophotographic imaging device generates pixel data bytes based upon data received from a computer defining an image. A converter generates codes specifying positions of transitions within a pixel time period corresponding to a pixel data byte. The transition placement device includes a phase measuring device to measure a timing offset between an active edge of a beam detect signal and a rising edge of a reference clock. A transition adjustment device adjusts the positions of the transitions specified by the codes relative to the rising edge of the reference clock using the timing offset. Transition generation logic generates the transitions for the stream of video data using the adjusted transition positions received from the transition adjustment device. If the adjusted positions of the transitions shift the occurrence of the transitions to the next cycle of the reference clock, the transition adjustment device determines the position of the transitions relative to the rising edge of the reference clock into which the transitions were shifted. Registers included in a next cycle transition storage device delay the transitions shifted to the next cycle by one reference clock cycle before application to the transition generation logic.