The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2002

Filed:

Jan. 16, 1997
Applicant:
Inventor:

Hiroshi Kanno, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9017 ;
U.S. Cl.
CPC ...
H03K 1/9017 ;
Abstract

Disclosed herein is a level conversion circuit which operates at high speeds even at a low power-supply voltage. The level conversion circuit is largely constituted by an emitter follower section , an amplitude amplification section , and a level conversion section . The amplitude amplification section is a differential amplifier constructed so that the gate of an N-channel MOS transistor M is connected to a node , the connection node of the drain is connected to a high power-supply terminal VCC through a resistor R , the source is connected to a node , the base of an N-channel MOS transistor M is connected to a reference power-supply terminal VR, the connection node of the drain is connected to the high power-supply terminal VCC through a resistor R , the source is connected to a node , the base of an NPN transistor Q is connected to a reference power-supply terminal VCSI, the collector is connected to the node , and the emitter is connected to the first low power-supply terminal GND through a resistor R


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