Method and system for dynamically locating frequently accessed memory regions or locations

Abstract

A method and system for monitoring the performance of a processor to detect a set of frequently accessed memory items is provided. A memory region to be monitored is selected and divided into an upper half monitored memory region and a lower half monitored memory region. Memory accesses to the upper half monitored memory region and memory accesses to the lower half monitored memory region are counted during a measurable interval. In response to the count of memory accesses to the upper half monitored memory region being greater than the count of memory accesses to the lower half monitored memory region, the monitored memory region is updated to be equal to the upper half monitored memory region. In response to the count of memory accesses to the lower half monitored memory region being greater than the count of memory accesses to the upper half monitored memory region, the monitored memory region is updated to be equal to the lower half monitored memory region. The steps of updating, dividing, and counting memory accesses to the monitored memory region during a measurable interval are repeated for a number of iterations in order to identify a frequently accessed memory region. As a set of instruction executes in the processor, a performance monitor may count the memory accesses and provide the numbers for optimization analysis.