Semiconductor memory based on address transitions

Abstract

A dynamic semiconductor memory device for writing/reading out data in/from a memory cell via a write/read circuit determined by a word line selected by a row address and a bit line selected by a column address, and temporally holding burst-written/read data by a data latch arranged on a data line connected to the write/read circuit includes an address transition detection circuit and a read-after-write circuit. The address transition detection circuit detects an address change to generate an operation start instruction signal, and starts a write/read cycle in accordance with the operation start instruction signal. The read-after-write circuit detects a change from a write mode to a read mode to generate a read-after-write instruction signal. When the read-after-write instruction signal is generated, data held by the write/read circuit is transferred to the data latch, and when the data is held by the data latch and read is done for the same row address, the data held by the data latch is read out and output. A semiconductor memory device manufacturing method is also disclosed.