Architecture for high speed memory circuit having a relatively large number of internal data lines

Abstract

An architecture for a high speed memory circuit having a relatively large number of internal data lines is shown to include global read and write data lines, and power and ground lines extending laterally across the array. The laterally extending lines are preferably within the third layer of metal. Preferably, the only other metal interconnect over the memory arrays is in the first metal layer, which is used to strap the word lines. Sense amp bands extend longitudinally along the borders of each memory cell bank. Local read and write data lines and read and write column select lines extend through the sense amp bands. Power and ground lines also extend through each sense amp band. Preferably, the architecture includes read path circuitry including a local read circuit that selectively isolates the global read data lines from the local read data lines. The architecture also preferably includes write path circuitry including a local write circuit that selectively isolates the global write data lines from the local write data lines. This architecture results in relatively low capacitance on the global read and write data lines, which permits faster data transfer speed with lower power requirements. It also results in relatively low resistance power and ground bussing, which further reduces the power requirements of the memory circuit.