The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2002
Filed:
Dec. 13, 1999
Tae-Song Chung, Danville, CA (US);
See-Hoi Caesar Wong, Fremont, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method and apparatus for optimizing crossover voltage for differential pair switches in a current-steering digital-to-analog converter or the like are disclosed. An array of at least one or more MOSFET switches may be utilized to control the crossover voltage of a differential pair of transistors such that the off time overlap of the differential pair transistors is optimized. In one embodiment, the pull-up and pull-down times of the input for the differential pair transistors are optimized such that the differential pair transistors are not turned off simultaneously. The array of switches may be n-channel MOSFETs when the differential pair are p-channel MOSFETs. Likewise, the array of switches may be p-channel MOSFETs when the differential pair are n-channel MOSFETs. The output of the diflerential pair is free of crossover glitches and is capable of being utilized in a data converter such as a current-steering digital-to-analog converter (DAC).