The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2002

Filed:

Feb. 02, 2000
Applicant:
Inventor:

Jayendar Rajagopalan, Santa Clara, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 4/06 ;
U.S. Cl.
CPC ...
H03K 4/06 ;
Abstract

A circuit for generating a ramped voltage having controlled maximum amplitude (e.g., for use in a switching controller), and a method for generating such a ramped voltage without use of a comparator. The ramped voltage is a voltage developed across a periodically charged and discharged capacitor, or optionally a level-shifted version of such voltage. Preferably, a ring oscillator generates a clock signal (without use of a comparator) for use in controlling the periodic charging and discharging of the capacitor, and a feedback loop generates a supplemental charging current for the capacitor in response to feedback indicative of the ramped output voltage. Preferably, the ring oscillator is a current-starved ring oscillator biased by a zero temperature coefficient bias current source, and the feedback loop includes a sample-adjust-hold circuit which samples the ramped output voltage shortly before the capacitor discharges, generates an adjustment voltage indicative of the difference between a reference voltage and the sampled output voltage, and holds the adjustment voltage for use in the next charging cycle. Preferably, a current mirror generates the supplemental charging current in response to the adjustment voltage held by the sample-adjust-hold circuit. The ramped voltage generation circuit can be implemented in less area (for the same ramped voltage frequency) than required for a conventional circuit employing at least one comparator, with the ramped voltage peak and valley levels being invariant to process and temperature variations, and with reduced supply voltage.


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