The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2002
Filed:
Sep. 25, 1998
Surya S. Bhattacharya, Irvine, CA (US);
Shyam Krishnamurthy, Los Angeles, CA (US);
Hong J. Wu, Irvine, CA (US);
Umesh Sharma, Newport Beach, CA (US);
Conexant Systems, Inc., Newport Beach, CA (US);
Abstract
A method of forming an improved interpoly oxide-nitride-oxide (ONO) stricture in stacked gate memory cells is provided. The top oxide layer of an interpoly ONO stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is greatly reduced. Steam densification of the TEOS layer produces a robust top oxide for the ONO dielectric, and thus, greatly reduces erosion of the top layer TEOS during subsequent processing steps (i.e., in the context of a memory array embedded in CMOS core technology). This step also tends to encourage formation of a very thin silicon oxynitride layer at the interface of the nitride and TEOS layers, thus helping to cure “pinholes” typically associated the nitride layer and further increasing the quality and reliability of the ONO structure. The improved interpoly ONO structure is found to show lower leakage current for applied electrice fields between 1 to 15 MV/cm as compared to prior art.