The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2002
Filed:
Jul. 23, 2001
Applicant:
Inventors:
Susumu Tanida, Hyogo, JP;
Masanori Hayashikoshi, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/14 ;
U.S. Cl.
CPC ...
G11C 7/14 ;
Abstract
A test mode reference potential generating circuit outputs a reference potential from an output node by activation of a test mode signal. When a sample signal is in an activated state, a transfer gate is turned on, and a capacitor stores the reference potential. When the test is being conducted, the transfer gate is turned off by inactivation of the sample signal, and thus the reference potential stored in the capacitor is output from a node. Thus, the semiconductor memory device according to the present invention can generate a stable reference potential during the test mode.