Technique for reducing the frequency of frame buffer clearing

Abstract

A clear color and count are stored in a frame buffer controller and in a video controller. The image buffer is cleared by writing the clear color into a color bit field and the count into a count bit field of each pixel. For each frame drawn, the count bit field of each pixel modified is updated with the count stored in the frame buffer controller. The counts stored in the frame buffer controller and the video controller are incremented with each new frame. When the counts reach maximum, the process repeats. Each time a pixel is read, the pixel's color bit field is replaced with the stored clear color if the pixel's count bit field is not equal to the stored count. The color bit field and the count bit field may be part of the same word of frame buffer memory. Or, the count value may be stored in an alpha bit field in lieu of an alpha value. If so, each time a pixel is read by the frame buffer controller, the pixel's count bit field may be replaced with a default alpha value stored in the frame buffer controller. Numerous pairs of clear count and clear color registers may be provided in the video controller, each pair corresponding to one window on the display. And numerous pairs of clear count and clear color registers may be provided in the frame buffer controller to better support double buffering and stereo operations.