The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2002
Filed:
May. 26, 1998
Noriko Shinomiya, Osaka, JP;
Masahiro Fukui, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
Method and apparatus for suppressing change in wiring delay time resulting from cell interchange and thereby satisfying required specifications in a short period of time with certainty during LSI layout designing. Cells are arranged in parallel to each other and routed based on circuit designing information, thereby designing a block layout including a plurality of cell rows. A cell not satisfying the required specifications is extracted from the block layout, and a level of drivability required for the cell to satisfy the required specifications is calculated. The extracted cell in question is interchanged with a substitute cell. The substitute cell has equivalent logic, a required level of drivability and the same width and terminal position in the cell arrangement direction reaction a cell row as the counterparts of the cell in question and is provided in a stretchable cell library.