Method and system for clock compensation in instruction level tracing in a symmetrical multi-processing system

Abstract

A method and system within a symmetrical multi-processing system or information handling system are disclosed for compensating all the processor clocks when performing instruction level tracing. The method provides a simple and flexible mechanism to slow down the clock proportionally to the density of the trace. According to the present invention, the method determines two parameters; a trigger and a compensation step. The trigger is defined as the number of instructions between clock increments and the compensation step is the number of ticks to add to a clock. When the trigger is equal to one, the clock is incremented at each tracing step by an amount equal to the compensation step multiplied by the number of instructions since the last compensation. When the trigger is greater than one, the compensation step is equal to one and the clock is incremented by one every time the number of instructions since the last compensation is bigger than the trigger. The method and system of the present invention links the trigger and compensation step together thereby allowing accurate clock compensation.