The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2002

Filed:

Apr. 06, 1999
Applicant:
Inventor:

Yung-soo Kim, Sungnam, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/30 ;
U.S. Cl.
CPC ...
H03H 7/30 ;
Abstract

A non-linear signal receiver. The non-linear signal receiver for detecting an original data a from an input signal r(t) which is a binary data stream input through a channel or reproduced from data recorded on a storing device includes: an analog-to-digital converter (ADC) for sampling the input value according to sampling timing phases, and converting the sampled data into a digital signal r ; a modeling portion including 2N+1 taps P (n=−N, . . . , 0, . . . , N) each for selecting one of 2 tap values according to each pattern p (b , b ) of absolute values of the data transitions future &ngr; bits and past &tgr; bits, for estimating the channel characteristics of the sampled signal from the selected tap value and the data transition value; a timing recovery portion for controlling the sampling timing phase of the analog-to-digital converter using a phase gradient equal to p ( )−p ( ), which is the difference between values of respective taps positioned symmetrically around the tap P of the modeling portion; an equalizer for compensating for the deteriorated characteristics of the output value of the analog-to-digital converter; and a detector for converting the output of the equalizer to a digital value, to detect the original signal. Therefore, an accurate timing phase can be found using a model in which a non-linear channel of a high-density digital magnetic storing device is expressed by transition pulses selected according to the future &ngr; bits and the past &tgr; bits, thereby reducing timing jitter and bias.


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