Semiconductor memory device provided with generating means for internal clock signal for special mode

Abstract

A semiconductor memory device is provided for reducing or preventing any switching to a special mode from a normal mode operation due to noise on an external clock without affecting any access time of the semiconductor memory device. In the semiconductor memory device, input buffer amplifiers converts a plurality of external clock signals into a plurality of internal clock signals each having an internal signal level, respectively, and then, a control clock signal generating circuit generates a control clock signal for controlling an operation of the semiconductor memory device in accordance with the plurality of internal clock signals. At least one of special mode input buffer amplifiers and noise filters has a time response characteristic gently changing according to a change in an input signal, and generates an internal clock signal for a different special mode from a normal mode associated with either one of reading and writing of data from and in the semiconductor memory device in accordance with at least one of the plurality of external clock signals.