The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2002

Filed:

Dec. 19, 2000
Applicant:
Inventors:

Soon Moon Jung, Gyeonggi-do, KR;

Sung Bong Kim, Gyeonggi-do, KR;

Joo Young Kim, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A method of forming contact holes of a semiconductor device wherein process yield is improved and manufacturing processes can be simplified. First, a plurality of gate electrodes provided with a plurality of spacers are formed on an active region of a semiconductor substrate that is separated into the active region and a field region by a field oxide layer. Then, the outermost spacers are removed from the plurality of spacers, to ensure a space for a first contact hole on the semiconductor substrate. Next, an etch stopping layer and an interlayer dielectric are subsequently formed on the semiconductor substrate. By etching the interlayer dielectric and the etch stopping layer subsequently, the first contact hole is formed by exposing a first surface of the semiconductor substrate between the gate electrodes and a second contact hole is formed by exposing a second surface of the semiconductor substrate which includes a portion of a surface of the field oxide layer and a portion of the semiconductor substrate near the field oxide layer, simultaneously. A manufacturing process of the semiconductor device can thus be simplified by forming contact holes simultaneously, using a self aligned contact method in which a first contact hole is formed by using a plurality of spacers and using a borderless contact method in which the second contact hole is formed from a side portion of the gate electrode to a portion of a field region.


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