The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2002

Filed:

Mar. 08, 2000
Applicant:
Inventor:

Kyung-Nam Lee, Kyungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/100 ;
Abstract

A gate wire including a gate line, a gate electrode and a gate pad, and a storage wire including a storage line and a storage electrode are formed on an insulating substrate. A gate insulating layer pattern, a semiconductor pattern made of amorphous silicon, and an ohmic contact layer pattern made of a doped amorphous silicon are patterned to have a shape covering the gate wire and the storage wire. Next, a transparent conductive layer made of ITO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad. A lower layer made of chromium having good contact properties with ITO and an upper layer made of either aluminum or aluminum alloy having low resistivity are sequentially deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode and a data pad. Next, the ohmic contact layer, which is not covered by the data wire, is etched. After forming the data wire, a passivation layer is formed and patterned to form contact holes respectively exposing the redundant gate pad and the redundant data pad, and an opening exposing the pixel electrode. To prevent the interference of image signals applied to adjacent data lines, the semiconductor pattern exposed through the opening of the passivation layer is removed. According to the present invention, because the pixel electrode of ITO is formed before forming the data wire, and the data wire has a double-layered structure including the lower layer of material having good contact properties with ITO and including also the upper layer of material having a low resistivity, wire damage and wire severance problems are prevented.


Find Patent Forward Citations

Lee, Kyung-Nam. (2002). Thin film transistor array panel for a liquid crystal display having a wide viewing angle and a method for manufacturing the same (U.S. Patent No. 6335211). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6335211

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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