The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2002

Filed:

Dec. 19, 2000
Applicant:
Inventors:

Seok Lyul Lee, Kyoungki-do, KR;

Jung Mok Jun, Seoul, KR;

Seung Min Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/00 ; G02F 1/1362 ;
U.S. Cl.
CPC ...
G03F 7/00 ; G02F 1/1362 ;
Abstract

Disclosed is a method for manufacturing a thin film transistor LCD device, in which a counter and a gate bus line are made in a single photolithography process, and a channel of a thin film transistor, a source electrode, a drain electrode, ohmic contacts for the source and drain electrodes are made in a single photolithography process. The method involves the steps of forming a first photoresist layer on said deposited metal layer for the gate bus line; exposing said first photoresist layer to a scanning light, so that the portion of the first photoresist layer disposed over a counter electrode region for forming said counter electrode may be partially lightened; patterning said first photoresist layer so that an area of the metal layer for the gate bus line lying under the partially lightened portion of the first photoresist layer may not be exposed; patterning said metal layer for the gate bus line by using said patterned first photoresist layer as a barrier layer so that said counter electrode region and a gate bus line region may be defined; patterning said transparent conductive layer for the counter electrode by using said patterned metal layer as a barrier layer so that said counter electrode may be formed; patterning said metal layer for the gate bus line by using said patterned first photoresist layer as a barrier layer so that said gate bus line may be formed.


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