Method and apparatus for in-system programming with a status bit

Abstract

Apparatus and method for programming a programmable logic device (PLD) using a status bit to indicate whether in-system programming (ISP) has been completed. Complex electronic systems often use PLDs to interface to other elements of the system and to the outside environment. Such PLDs are reprogrammed by the system controller using the boundary-scan/JTAG access port, but a power failure may cause an unwanted termination of the programming cycle before all of the PLD internal logic, connections, and functional I/O pins are properly programmed. In such a situation, some or all of the PLD functional (input/output) pins could be driven to erroneous states such that other devices connected to them would be damaged or prevented from operating correctly. The status indicator is set to hold all PLD functional pins in a high impedance condition (tri-state) until programming or another non-mission mode of PLD operation is successfully concluded. Additionally, selected driver elements within the PLD can be disabled in the same way. In the event of an unexpected loss of power, the status indicator causes all PLD functional pins to come up in tri-state on restoration of power and therefore be unable to assert control of any other connected devices or busses. Likewise, selected drivers can also be disabled to prevent similar contention problems.