Testable integrated circuit, integrated circuit design-for-testability method, and computer-readable medium storing a program for implementing the design-for-testability method

Abstract

Apparatus for testing integrated circuits containing a controller or other sequential circuit at actual operating speed while minimizing the length of the test sequence and achieving high fault coverage are provided. The states of a state register are assumed controllable and observable, and a set of test patterns is obtained for a combinational circuit not containing said state register. An invalid-state generation logic circuit is added for generating invalid states, which are states contained in the generated test patterns but cannot be set by a normal transition from the reset state. A multiplexer is added for selecting the output of a next-state generation logic circuit or the invalid-state generation logic circuit for input to the state register based on a state transition mode selection signal. Signals corresponding to pseudo-primary outputs during test generation are made observable, and the multiplexer output signal is externally detectable as a state output signal.