Method and arrangement for controlling multiply-activated test access port control modules

Abstract

An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled at a time. For applications typically requiring that control be transferred between such TAP controllers, one embodiment of the present invention configures a TLM-based design such that multiple TAP controllers can be simultaneously enabled. This alleviates the need to actually transfer the control from one TAP controller to the next. To maintain consistency with the IEEE JTAG recommendation, the TLM-based design is configured such that only one TAP is enabled upon reset. After reset, the TLM controls the multiply-enabled TAP controllers. Another specific example implementation is directed to a circuit control arrangement for such a multi-core IC having each TAP controller generate status and test signals in response to input signals directed to each of the multiple TAP controllers. A TAP link arrangement, including a TAP link module and control signals coupled to each of the multiple TAP controllers, selectively multiplexes the input signals to the multiple TAP controllers and multiplexes the status and test signals provided by the multiple TAP controllers to an output port of the IC.