Clock synchronous semiconductor device having a reduced clock access time

Abstract

In an output data control circuit for transferring complementary data signals read from a memory array to an external data output node in accordance with an output clock signal, a clocked gate circuit transferring complementary data signals in synchronization with an output clock signal and an output data latch circuit latching an output signal of the clocked gate circuit are operated using a voltage level not exceeding an internal power supply voltage, and the complementary data signals read from a memory cell is subjected to an amplitude expanding processing in a stage preceding the clocked gate circuit, and then is applied to the clocked gate circuit. A clock synchronous semiconductor memory device allowing reduction of a clock access time is provided.