Memory device with a plurality of common data buses

Abstract

According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area. According to the present invention, there is provided a memory device having a plurality of banks each including a plurality of memory cells, and reading or writing data from or into the memory cells in synchronism with a clock signal, the memory device comprising: a sense amplifier disposed on each of the plurality of banks, for amplifying data read from the memory cells; a plurality of common data buses shared by the plurality of banks, the number of the common data buses being less than the number of the banks; and a switching circuit disposed on each of the plurality of banks, for feeding or receiving data of the each bank to or from the plurality of common data buses; wherein read or write of data of the plurality of banks is made through successive selection of the plurality of common data buses by the switching circuit.