The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2001

Filed:

Jun. 16, 2000
Applicant:
Inventor:

Thomas Harju, Sävedalen, SE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/06 ;
U.S. Cl.
CPC ...
H05K 7/06 ;
Abstract

The present invention relates to an arrangement concerned with multilayer printed circuit boards that enables cavities in said board to be utilized more effectively. A substrate (,) that includes a chip (,) which is connected to the microstrips (,) of the substrate (,) by means of bonding wires (,) is placed on a bonding shelf (,) with the chip (,) orientated towards the bottom of the cavity (,). The microstrips (,) on the substrate (,) therewith come into contact with the microstrips (,) on the bonding shelf (,). The earth plane (,) of the substrate (,) is connected to the upper earth plane (,) by means of bonding wires (,). The arrangement means that the cavity (,) is utilized effectively, at the same time as the substrate (,) protects the underlying chips (,) against mechanical influences.


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Harju, Thomas. (2001). Arrangement for mounting chips in multilayer printed circuit boards (U.S. Patent No. 6333856). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6333856

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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