The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2001

Filed:

Aug. 06, 1999
Applicant:
Inventors:

Hiroomi Nakajima, Yokohama, JP;

Toshihiro Sakamoto, Kitakyushu, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/978 ; H01L 2/7102 ; H01L 2/7082 ;
U.S. Cl.
CPC ...
H01L 2/978 ; H01L 2/7102 ; H01L 2/7082 ;
Abstract

This invention includes a semiconductor substrate of one conductivity type having a semiconductor layer of an opposite conductivity type from an upper surface to a predetermined depth and first and second projections on the semiconductor layer of the opposite conductivity type, a first insulating film formed on an upper surface of the semiconductor substrate of one conductivity type from a portion except for the first and second projections to a predetermined level not reaching upper surfaces of the first and second projections, a semiconductor film of one conductivity type formed on at least the upper surface of the first projection, a first semiconductor film of the opposite conductivity type formed on at least the upper surface of the second projection, and a second semiconductor film of the opposite conductivity type formed in a predetermined position on an upper surface of the semiconductor film of one conductivity type. This structure allows an emitter to be formed without any alignment. In this invention, a p-type silicon layer corresponding to a base region and an n-type silicon layer corresponding to an emitter region are formed to be self-aligned with an element region (n-type heavily doped impurity region) corresponding to a collector layer. This makes alignment margin between these regions unnecessary and reduction of the element area possible. Unlike in conventional devices, almost no parasitic capacitances exist between an emitter electrode and a base electrode. This achieves high operating speed.


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