The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2001
Filed:
Dec. 26, 2000
Jeffrey S. Earl, San Jose, CA (US);
Vanguard International Semiconductor Corporation, Hsin-Chu, TW;
Abstract
Described is a method for verification of proper address generation in packet based memory protocol (Direct RDRAM) devices during the auto-refresh or self-refresh cycle that does not require changes to the interface logic or core signal generation. The method requires minimal additional logic while using the core control signals that function similarly to the RAS, CAS, and WE signals in a standard DRAM. Initially, high level (,) data are written to all of the memory cells of one bit line. The signals are manipulated, and a refresh is performed. As each memory cell is addressed during the refresh, the data are changed to a low level (,). Addressing is then verified by observing the data stored in the memory cells and confirming that a low level (,) is now stored. The method may be extended to standard DRAM devices.