The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2001
Filed:
Nov. 29, 2000
Kazuhiko Sanada, Tokyo, JP;
Kenji Saitou, Tokyo, JP;
Kiyokazu Ishige, Tokyo, JP;
Hitoshi Nakamura, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data erase in the memory cells of the group.