The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2001
Filed:
May. 12, 1999
Shye-Lin Wu, Hsinchu, TW;
Abstract
In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed and is communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer. Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer. A hemispherical grained silicon layer is then formed on the first conductive layer. A fourth dielectric layer is formed on the substrate over the hemispherical grained silicon layer and the first conductive layer, and the substrate is planarized to the surface of the third dielectric layer. The fourth dielectric layer and the third dielectric layer are then removed to leave a storage node which is composed of the first conductive layer and the hemispherical grained silicon layer. Finally, a fifth dielectric layer is formed on the storage node, and a second conductive layer is then formed on the fifth dielectric layer to finish the capacitor structure.