The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2001
Filed:
Mar. 31, 1998
Ron Abramov, Brookline, MA (US);
Mary T. Donnellan, Milford, MA (US);
EMC Corporation, Hopkinton, MA (US);
Abstract
Apparatus for testing a data storage system. The system includes an interface adapted for disposition between a host computer and a disk drives. The interface has a controller and an addressable memory interconnected through a bus. The system operates asynchronously in transferring data between the controller and the memory. The testing apparatus includes a generator for injecting an electrical disturbance into a predetermined point in the interface during a selected state when data is transferred between the memory and the controller. The disturbance is initiated in response to an actuation signal. A storage medium is provided for storing the state. A comparator is provided for monitoring current operating state of the interface and the selected state stored in the storage medium and for producing the activation signal when the current operating state of the system and the selected operating state have a predetermined relationship. The generator produces the disturbance from a source having an predetermined output impedance and the testing apparatus includes a buffer disposed between the generator and the interface for transforming the predetermined output impedance to a higher output impedance until the disturbance is injected into the system. The higher output impedance is selected to prevent current flow between the source and the point of the interface. The disturbance has a time duration less that the time duration of the transfer of the data between the memory and the controller.