Cache memory system with memory request address queue, cache write address queue, and cache read address queue

Abstract

A cache memory system includes a main memory controller for retrieving memory data from a main memory unit, a cache memory for writing the memory data retrieved by the main memory controller therein, and a tag memory module for detecting presence of a cache hit condition, indicating that an address signal received thereby has a corresponding data entry in the cache memory, or a cache miss condition, indicating a need for accessing the main memory unit. An address queue of a read data controller receives a cache memory address corresponding to the address signal from the tag memory module, and provides the cache memory address to the cache memory to control reading of the memory data from the cache memory. An address queue of a data request controller receives a main memory address and the cache memory address that correspond to the address signal from the tag memory module in the event of the cache miss condition, and provides the main memory address to the main memory controller to control retrieval of the memory data from the main memory unit. An address queue of a write data controller receives the cache memory address from the data request controller, and provides the cache memory address to the cache memory to control writing of the memory data in the cache memory.