The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2001

Filed:

Feb. 08, 2000
Applicant:
Inventors:

Tetsuo Kato, Hyogo, JP;

Takayuki Miyamoto, Hyogo, JP;

Tetsushi Tanizaki, Hyogo, JP;

Mikio Asakura, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 2/900 ;
U.S. Cl.
CPC ...
G11C 2/900 ;
Abstract

A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.


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