The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2001
Filed:
Dec. 27, 1999
Danny Pak-Chum Shum, Austin, TX (US);
Juan Buxo, Austin, TX (US);
John P. Hansen, Austin, TX (US);
Scott W. Krueger, Leander, TX (US);
James David Burnett, Austin, TX (US);
Eric Johan Salter, Scottsdale, AZ (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
A semiconductor device having a memory array includes memory cells (,), a word line (,), a first bit line (,), and a second bit line (,). Within the memory array, the first and second bit lines (,and,) lie at different elevations above the word line (,). Local interconnects (,) are electrically connected to the first bit line (,) and some of the current carrying electrodes (,) in the memory array. The local interconnects (,) allow offset connections to be made. For floating gate memory cells (,) in a NOR-type memory array architecture, programming and erasing can be performed using a relatively uniform bias between the source and drain regions (,and,) of a memory cell (,) to be programmed without significantly disturbing data in adjacent floating gate memory cells (,).