The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2001
Filed:
Jan. 28, 2000
James W. Miller, Austin, TX (US);
Michael G. Khazhinsky, Austin, TX (US);
Geoffrey B. Hall, Austin, TX (US);
Jose A. Camarena, Austin, TX (US);
Joseph Chan, Round Rock, TX (US);
Fujio Takeda, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A circuit (,) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (,) includes cascoded NMOSFETs (,), with the upper NMOSFET (,) connected to voltage divider circuitry (,). The voltage divider circuitry (,) provides a first bias voltage to the gate of the upper NMOSFET (,) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately,of the drain voltage of the upper NMOSFET (,). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.