The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2001
Filed:
Dec. 22, 1999
Roy A. Colclaser, Albuquerque, NM (US);
Neil Morris, Albuquerque, NM (US);
Philips Electronics North America Corporation, New York, NY (US);
Abstract
An integrated circuit includes electrostatic discharge (ESD) protection circuits coupled to protect I/O pins and or operational circuits from damage due to ESD events. The ESD protection circuits are coupled to fuses which in turn are coupled to external program pin(s) of the IC. The fuses can be opened via the external program pin(s) to substantially completely remove the capacitive loading on the I/O pins as well as any internal circuitry within the IC. The ESD circuits may protect against ESD damage during testing, packaging, shipping and installation into a system, and then be subsequently removed via the external program pins, such as upon first application of power to the IC via the system. Because fuses are used, the added capacitive loading of the deselection circuit is substantially zero and much less than active switching elements. The ESD deselection structure is beneficial for very high frequency RF circuits, where capacitive loading problems are particularly acute.