The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2001
Filed:
Apr. 11, 2000
Applicant:
Inventor:
Brian Paul Brandt, Windham, NH (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/45 ;
U.S. Cl.
CPC ...
H03F 3/45 ;
Abstract
A differential amplifier and method including a differential pair of input MOS transistors coupled to a common tail current source and a pair of MOS load transistors, with the amplifier outputs being disposed intermediate the input and load transistors. Biasing circuitry is included to maintain the load transistors in the linear region of operation. Reset transistors can be used to periodically reset the amplifier by connecting the outputs directly to the inputs.
Brandt, Brian. (2001). Low voltage fet differential amplifier and method (U.S. Patent No. 6326846). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6326846
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile