The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2001

Filed:

Sep. 04, 1998
Applicant:
Inventors:

Terry R. Bloom, Middlebury, IN (US);

Stephen W. Burry, Berne, IN (US);

Lewis L. Seffernick, Decatur, IN (US);

Robert M. VandenBoom, Markle, IN (US);

John Zdanys, Jr., Elkhart, IN (US);

Assignee:

CTS Corporation, Elkhart, IN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 1/01 ; H01L 2/358 ; H01P 1/24 ; H05K 1/16 ;
U.S. Cl.
CPC ...
H01L 1/01 ; H01L 2/358 ; H01P 1/24 ; H05K 1/16 ;
Abstract

A ball grid array resistor network has a substrate that has top and bottom surfaces. Resistors are disposed on the top surface. Conductors are disposed on the top surface, and each conductor is electrically connected to an end of each resistor. Vias extend through the substrate and are electrically connected to the conductors. Solder spheres are disposed on the bottom surface, and are electrically connected to the vias. A cover coat is disposed over the conductors and resistors. In an alternative embodiment, the vias are eliminated and the resistor network is formed on the bottom surface of the substrate. The resistor network provides a high density of resistors per unit area.


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