The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2001

Filed:

Aug. 23, 1999
Applicant:
Inventors:

Mark S. Rodder, University Park, TX (US);

Jorge A. Kittl, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/14763 ;
Abstract

An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming the gate structure over the substrate (step,of FIG.,); forming a source/drain regions and a channel region in the semiconductor substrate (step,), the channel region situated between the source/drain regions and under the gate structure; forming a photoresist layer over the source/drain regions (step,); amorphizing a portion of the gate structure by introducing an amorphizing substance into the gate structure (step,); removing the photoresist layer after the step of amorphizing a portion of the gate structure step,); forming a metal layer on the conductive structure, the metal layer interacts with the gate structure in the amorphized portion of the gate structure and the source/drain regions so as to form a lower resistivity silicide on the gate structure and the source/drain regions (step,); and wherein the photoresist layer blocks the amorphizing substance from the source/drain regions and allows the amorphizing substance to enter the gate structure.


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