Methods for manufacturing field emitter arrays on a silicon-on-insulator wafer

Abstract

The present invention provides methods for manufacturing field emitter arrays on a silicon-on-insulator (SOI) wafer, one of which comprising steps of forming a doped silicon layer by doping a dopant on a single crystalline silicon layer of an SOI wafer; making a buffer oxide layer on the doped silicon layer; making a stripe pattern of silicon nitride on the buffer oxide layer; etching the buffer oxide layer using the stripe pattern as a mask; etching the doped silicon layer anisotropically using the stripe pattern as a mask; making a minute mask pattern of silicon nitride on the buffer oxide layer by patterning the stripe pattern of silicon nitride; selectively oxidizing the upper part of the doped silicon layer to form an oxide layer except on the portions under the mask pattern; etching away the mask pattern of silicon nitride and the buffer oxide layer deposited under the mask pattern; etching away the exposed doped silicon layer for making gate holes of undercut shape; forming metal layers on the SOI wafer and the bottom of the gate holes by evaporating a metallic evaporant downwardly and vertically against the surface of the SOI wafer; and forming the field emitter tips on the metal layer in the gate holes. According to the present invention, electrical isolation between one cathode line and the other may be accomplished without any junction isolation step and an extremely small size of the field emission elements may be formed uniformly over a large area.