The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2001

Filed:

Jan. 27, 1999
Applicant:
Inventors:

William D. Farwell, Thousand Oaks, CA (US);

Robert L. Stokes, Redondo Beach, CA (US);

Assignee:

Raytheon Company, Lexington, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract

A test circuit that includes a scan path having serially coupled scan flip-flops clocked by a system clock signal, an index counter clocked by the system clock for providing an index output for tracking data in the scan path, a control circuit clocked by a test clock signal for receiving scan input data from an external source and for providing output data to the external source, an input memory for receiving scan input data from the control circuit, an output memory for receiving the output of the scan path, and a selection circuit having a first input for receiving the output of the scan path, a second input for receiving scan input data from the input memory, and an output connected to the input of the scan path.


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Farwell, William. (2001). Means for testing dynamic integrated circuits (U.S. Patent No. 6324664). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6324664

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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