Branch prediction and target instruction control for processor

Abstract

A two level branch prediction system and method is disclosed for controlling instruction flow in a pipelined processor. A first prediction indicator associated with a branch instruction specifies whether a particular branch condition is likely to be satisfied. A second prediction indicator associated with a branch control instruction specifies whether a particular branch target instruction is likely to be needed by one or more of the branch instructions. The first prediction indicator is used to load branch target instructions as they are needed in response to decoding a branch instruction, while the second prediction indicator is used by prefetching logic within the processor to determine whether a particular branch target instruction should be speculatively loaded even before the associated branch instruction is executed. The first and second prediction indicators can be set in advance as bit fields in the branch and branch control instructions respectively so that the processor microarchitecture behavior can be set up and controlled in software to reduce branch latencies for a particular program. The second prediction indicators can be ranked as well so that the prefetching logic can prioritize speculative loadings in accordance with a desired strategy.