The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2001

Filed:

Apr. 13, 2001
Applicant:
Inventors:

George Z. Chrysos, Milford, MA (US);

Wilson P. Snyder, II, Hudson, MA (US);

Assignee:

Compaq Computer Corporation, Houston, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/318 ;
U.S. Cl.
CPC ...
G06F 1/318 ;
Abstract

A method of limiting, in a digital processor, low-priority utilization of a resource in favor of high-priority utilization of the resource comprises determining a value predictive of high-priority utilization of the resource. Low-priority utilization of the resource is inhibited if the determined predictive value is greater than a threshold. On the other hand, if the predictive value is less than or equal to the threshold, then low-priority utilization of the resource is allowed. In a preferred embodiment, the predictive value is derived by counting the number of actual high-priority utilizations of the resource out of the last N opportunities in which the resource could have been utilized for a high-priority need. Preferably, recent utilizations are given more weight than others. In a preferred embodiment, the resource comprises one of main memory, instruction cache memory, or data cache memory. High-priority utilization comprises high-priority access to memory and low-priority utilization comprises memory prefetching. Low priority utilizations are throttled when the threshold is exceeded. Counting and comparing are done with a shift register, counting logic, and a comparator; or with a counter and a comparator; or with two shift registers in which case no comparator is needed.


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