The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2001
Filed:
Sep. 23, 1999
Mitsuo Ukechi, Tokyo, JP;
Takuya Miyashita, Tokyo, JP;
Japan Aviation Electronics Industry Limited, Tokyo, JP;
Abstract
The surface area of a rectangular semiconductor substrate (,), which is used a reference plane, is composed of three regions arranged side by side in its lengthwise direction. A first one of the regions has a concavity (,) formed leaving opposite marginal portions of the region as banks (,), aid solder-coated pads (,) and alignment marks (,) are formed by metal thin films on the top surfaces of the banks. In a second region an electrode (,) is formed adjacent the first region and a semiconductor optical element (PD,) is mounted on the electrode with an active layer (,) of the former facing downward. An under-clad layer (,), acore (,), a height adjustment layer (,) and an over-clad layer (,), which constitute an optical waveguide, are formed over the surface of a second substrate, and the over-clad layer overlying both marginal portions of the second substrate is removed to expose the height adjustment layer to form terraces (,) corresponding to the banks. Solder-coated pads (,) and alignment marks (,) are formed by metal films on the terraces, and the solder-coated pads (,) and (,) are soldered to each other with the banks and the terraces positioned using the alignment marks (,) and (,). The thickness of the height adjustment layer (,) is predetermined so that the core and the semiconductor active layer (,) lie at the same vertical position relative to the reference plane.