The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2001
Filed:
Oct. 05, 1998
Yi-Sern Lai, Tainan Hsien, TW;
I-Yao Chuang, Taipei, TW;
Bor-Wen Chiou, Tau-Yuan Hsien, TW;
Chin-Ning Yang, Shin-Chu, TW;
Industrial Technology Research Institute, Chu-Tuan Chen, TW;
Abstract
A full duplex DES cipher processor (DCP) supports to execute sixteen rounds of data encryption standard (DES) operation in four encryption modes and four decryption modes, namely: Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback (CFB) mode, and Output Feedback (OFB) mode for both encryption and decryption. A DCP is composed of an I/O unit, an IV/key storage unit, a control unit, and an algorithm unit. The algorithm unit is used to encrypt/decrypt the incoming text message. The algorithm unit having a crypto engine allows encryption and decryption performed alternately, by sharing the same crypto engine. Since for crypto applications in communication services like T1, E1, V.35, the algorithm unit operation time is much shorter than the data I/O time; in other word, the algorithm unit is in the idle state mostly. The full duplex operation is achieved by storing the interim results of the DES encryption operation in a cipher text buffer (CTB) and the decryption results in a plain text buffer (PTB), where the CTB and PTB are in the crypto engine. The full duplex DCP has two ports, one for encrypting and the other for decrypting. In addition, the DCP can also be used for single port simplex or dual port simplex applications.