The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2001
Filed:
Feb. 17, 2000
Meei-Ling Chiang, San Jose, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A pipeline analog to digital (A/D) converter having a sample and hold stage which samples an analog input signal during a primary clock signal and holds during a secondary clock signal. The A/D converter has an analog signal converter stage which converts and latches the sampled and held voltage signal into a digital output during the secondary clock signal. The analog signal converter stage generating a residue signal based on a comparison of the sampled and held voltage signal and from an analog representation of the digital output, the analog signal converter stage samples the sampled and held voltage signal during the secondary clock signal and holds the residue signal during the primary clock signal. The primary and secondary clock signals together form a two phase nonoverlapping clock having a regular period with a length defined by the duty cycles of the primary and secondary clock signals. The duty cycle of the primary clock signal being less than the duty cycle of the secondary clock signal. According to another aspect of the invention, an A/D converter has a sample and hold stage which samples an analog input signal during a first clock signal and holds a sampled voltage signal during a second clock signal. The A/D converter has an analog signal converter stage, which converts and latches the sampled and held voltage signal into a digital output during the second clock signal. The analog signal converter stage generating a residue signal based on a comparison of the analog input signal and from an analog representation of the digital output, the analog signal converter stage samples the analog input signal during the first clock signal and holds the residue signal during a third clock signal. The first clock signal and the second clock signal form a first two phase nonoverlapping clock and the third clock pulse signal forms a second two phase nonoverlapping clock with a fourth clock pulse signal. The fourth clock signal having a duty cycle of less than, greater than or equal to 50% of the period of the second nonoverlapping clock, and the pulse of the first clock signal and the pulse of the second clock signal both overlapping with the pulse of the fourth clock signal. The duty cycle of the first clock signal is optionally less than the duty cycle of the second clock signal.